feat(serial): add serial initialization
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Signed-off-by: Julien CLEMENT <julien.clement@epita.fr>
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@ -11,8 +11,18 @@ const COM3: u16 = 0x3e8;
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#[allow(dead_code)]
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const COM4: u16 = 0x2e8;
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const ENABLE_TRANSMITTER: u8 = 0x1 << 1;
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const FIFO: u8 = 0x1;
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const TRIGGER_LVL_14: u8 = 0x3 << 6;
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const CLEAR_TRANSMIT_FIFO: u8 = 0x1 << 2;
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const CLEAR_REVEIVE_FIFO: u8 = 0x1 << 1;
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const NO_PARITY: u8 = 0x0;
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const EIGHT_BITS_LENGTH: u8 = 0x3;
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const EMPTY_TRANSMITTER: u8 = 0x1 << 5;
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const DLAB: u8 = 0x1 << 7;
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lazy_static! {
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pub static ref SERIAL1: Mutex<SerialPort> = {
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@ -50,6 +60,9 @@ macro_rules! serial_println {
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pub struct SerialPort {
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base: Port<u8>,
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interrupt_enable: Port<u8>,
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fifo_control: Port<u8>,
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line_control: Port<u8>,
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line_status: Port<u8>,
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}
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@ -57,6 +70,9 @@ impl SerialPort {
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pub fn new(port: u16) -> SerialPort {
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SerialPort {
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base: Port::new(port),
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interrupt_enable: Port::new(port + 1),
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fifo_control: Port::new(port + 2),
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line_control: Port::new(port + 3),
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line_status: Port::new(port + 5),
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}
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}
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@ -86,7 +102,26 @@ impl SerialPort {
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len
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}
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fn init(&mut self) {}
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fn init_baud_rate(&mut self) {
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let line: u8;
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unsafe {
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line = self.line_control.read();
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self.line_control.write(line | DLAB);
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self.base.write(3);
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self.interrupt_enable.write(0);
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self.line_control.write(line);
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}
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}
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fn init(&mut self) {
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self.init_baud_rate();
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unsafe {
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self.line_control.write(NO_PARITY | EIGHT_BITS_LENGTH);
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self.fifo_control
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.write(FIFO | TRIGGER_LVL_14 | CLEAR_TRANSMIT_FIFO | CLEAR_REVEIVE_FIFO);
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self.interrupt_enable.write(ENABLE_TRANSMITTER);
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}
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}
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}
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impl fmt::Write for SerialPort {
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@ -94,7 +129,7 @@ impl fmt::Write for SerialPort {
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let len: usize = self.write_string(s);
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match len {
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l if l == s.len() => Ok(()),
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_ => Err(fmt::Error)
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_ => Err(fmt::Error),
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}
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}
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}
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