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No commits in common. "bec3630c1119a26cbd6b2c45659a34078ff02535" and "b9557bdc5ec6f8f3cc98fb9ed03dc44eb0636d86" have entirely different histories.

2 changed files with 13 additions and 70 deletions

@ -1,8 +1,8 @@
#![no_std] #![no_std]
#![no_main] #![no_main]
mod serial;
mod vga; mod vga;
mod serial;
use core::panic::PanicInfo; use core::panic::PanicInfo;
use vga::Color; use vga::Color;
@ -15,7 +15,8 @@ fn panic_handler(info: &PanicInfo) -> ! {
#[no_mangle] #[no_mangle]
pub extern "C" fn julios_main() -> ! { pub extern "C" fn julios_main() -> ! {
println!("***JuliOS V0.1.0***"); println!("Hello World!");
serial_println!("Hello serial"); println!("{}", "***JuliOS***");
serial_println!("Test serial");
panic!("Kernel end of flow"); panic!("Kernel end of flow");
} }

@ -1,6 +1,6 @@
use core::fmt; use core::fmt;
use lazy_static::lazy_static;
use spin::Mutex; use spin::Mutex;
use lazy_static::lazy_static;
use x86_64::instructions::port::Port; use x86_64::instructions::port::Port;
const COM1: u16 = 0x3f8; const COM1: u16 = 0x3f8;
@ -11,19 +11,6 @@ const COM3: u16 = 0x3e8;
#[allow(dead_code)] #[allow(dead_code)]
const COM4: u16 = 0x2e8; const COM4: u16 = 0x2e8;
const ENABLE_TRANSMITTER: u8 = 0x1 << 1;
const FIFO: u8 = 0x1;
const TRIGGER_LVL_14: u8 = 0x3 << 6;
const CLEAR_TRANSMIT_FIFO: u8 = 0x1 << 2;
const CLEAR_REVEIVE_FIFO: u8 = 0x1 << 1;
const NO_PARITY: u8 = 0x0;
const EIGHT_BITS_LENGTH: u8 = 0x3;
const EMPTY_TRANSMITTER: u8 = 0x1 << 5;
const DLAB: u8 = 0x1 << 7;
lazy_static! { lazy_static! {
pub static ref SERIAL1: Mutex<SerialPort> = { pub static ref SERIAL1: Mutex<SerialPort> = {
let mut serial_port = SerialPort::new(COM1); let mut serial_port = SerialPort::new(COM1);
@ -35,10 +22,7 @@ lazy_static! {
#[doc(hidden)] #[doc(hidden)]
pub fn _print(args: ::core::fmt::Arguments) { pub fn _print(args: ::core::fmt::Arguments) {
use core::fmt::Write; use core::fmt::Write;
SERIAL1 SERIAL1.lock().write_fmt(args).expect("Printing to serial failed");
.lock()
.write_fmt(args)
.expect("Printing to serial failed");
} }
/// Prints to the host through the serial interface. /// Prints to the host through the serial interface.
@ -60,76 +44,34 @@ macro_rules! serial_println {
pub struct SerialPort { pub struct SerialPort {
base: Port<u8>, base: Port<u8>,
interrupt_enable: Port<u8>,
fifo_control: Port<u8>,
line_control: Port<u8>,
line_status: Port<u8>,
} }
impl SerialPort { impl SerialPort {
pub fn new(port: u16) -> SerialPort { pub fn new(port: u16) -> SerialPort {
SerialPort { SerialPort {
base: Port::new(port), base: Port::new(port)
interrupt_enable: Port::new(port + 1),
fifo_control: Port::new(port + 2),
line_control: Port::new(port + 3),
line_status: Port::new(port + 5),
} }
} }
fn write_byte(&mut self, byte: u8) -> bool { fn write_byte(&mut self, byte: u8) {
unsafe { unsafe {
let status: u8 = self.line_status.read();
match status & EMPTY_TRANSMITTER {
0 => false,
_ => {
self.base.write(byte); self.base.write(byte);
true
}
}
} }
} }
fn write_string(&mut self, s: &str) -> usize { fn write_string(&mut self, s: &str) {
let mut len: usize = 0;
for byte in s.bytes() { for byte in s.bytes() {
let written: bool = self.write_byte(byte); self.write_byte(byte);
if !written {
return len;
}
len += 1;
}
len
}
fn init_baud_rate(&mut self) {
let line: u8;
unsafe {
line = self.line_control.read();
self.line_control.write(line | DLAB);
self.base.write(3);
self.interrupt_enable.write(0);
self.line_control.write(line);
} }
} }
fn init(&mut self) { fn init(&mut self) {
self.init_baud_rate();
unsafe {
self.line_control.write(NO_PARITY | EIGHT_BITS_LENGTH);
self.fifo_control
.write(FIFO | TRIGGER_LVL_14 | CLEAR_TRANSMIT_FIFO | CLEAR_REVEIVE_FIFO);
self.interrupt_enable.write(ENABLE_TRANSMITTER);
}
} }
} }
impl fmt::Write for SerialPort { impl fmt::Write for SerialPort {
fn write_str(&mut self, s: &str) -> fmt::Result { fn write_str(&mut self, s: &str) -> fmt::Result {
let len: usize = self.write_string(s); self.write_string(s);
match len { Ok(())
l if l == s.len() => Ok(()),
_ => Err(fmt::Error),
}
} }
} }